1. Field of the Invention
The present invention relates to an external storage device of a computer using, for example, a static storage device, and more particularly relates to an external storage device for processing error detection and error correction of sector data at a high speed when sector data having an arbitrary byte width are accessed continuously according to a size of a sector unit.
2. Description of Related Art
With regard to background art, in order to simultaneously realize an improvement in reliability and high speed access in memory control, as disclosed in Japanese Patent Laid-Open No. Hei 6-105443 (1994), there is a system where data of an x-byte width outputted from a memory are divided into an odd number part (x/2 byte width) and an even number part (x/2 byte width), and regarding each of the odd number part and the even number part, error detection and error correction are performed using error correcting codes, and data of an x/2 byte width as outputted from the odd number part and the even number part are continuously outputted to a system bus of an x/2 byte width by an interleave control method.
In order to perform the error detection and the error correction for sector data having an m-byte (e.g., 512 byte) width, the sector data of an m-byte width must be divided into an n-byte (e.g., one byte) unit for m/n times (m is a multiple of n) and then inputted to error correcting means.
However, since error detection and error correction in the background art as described above are performed for data having a same byte width as that of the system bus, a differing byte arrangement cannot be applied as it is to error detection and error correction for sector data having an m-byte width larger than the byte width of the system bus. Moreover, as a further disadvantage in the background art as above described, both the odd number part and the even number part require individual error correcting means.
The teachings of each of any above- or below-listed art are herein incorporated by reference.
An object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced when error detection and error correction are performed for sector data having an m-byte width larger than the byte width of the system bus, and to realize a memory access at a high speed.
Another object of the present invention is to provide an external storage device where a time required for error detection and error correction is reduced using a single error correcting means, and to realize a memory access at a high speed.
In order to attain the foregoing objects, the present invention provides an external storage device comprising: a system interface section for conducting an interface with a host computer; error correcting means for performing error detection and error correction for sector data constituted by data having a byte number larger than that of a bus width of a system bus connecting the system interface section and the host computer; a first memory and a second memory as static storage devices each having a memory bus with a same bus width as that of the system bus for storing sector data; and control means for controlling a reading and writing operation of sector data from the host computer to the first memory and the second memory, wherein in response to a write command from the host computer, the control means stores a plurality of sector data attendant on the write command in the size of a sector unit alternately in the first memory and the second memory, and in response to read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the first memory and supplies the read-out sector data to the error correcting means, and then the control means reads out the sector data of the first memory and the second memory simultaneously, so that while the N-th (where N is a natural number) sector data from one of the first memory and the second memory are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.
In this preferred external storage device, data changing means selectively connects the memory bus of the first memory to one of the system interface section and the error correcting means, and also selectively connects the memory bus of the second memory to the other, and during the read access from the host computer, the control means alternately controls the data changing means so as to selectively and alternately read out the sector data of the first memory and the second memory.
In a write access of sector data from the host computer to the first and second memories, a write buffer for temporarily storing the sector data may be provided to effect storage of the sector data in the first and second memories through the write buffer.
In another embodiment, in place of the first memory and the second memory, a memory having a memory bus width of twice that of the system bus for storing sector data may be used. In this case, in response to write command from the host computer, the control means stores odd-numbered sector data (among a plurality of sector data) attendant on the write command using, for example, an upper side of the memory bus and memory, and also stores even-numbered sector data using, for example, a lower side of the memory bus and memory. In response to a read command from the host computer, the control means reads out the first sector data among a plurality of sector data required by the read command from the upper side of the memory and supplies the readout sector data to the error correcting means, and then the control means reads out the sector data at the upper side and the lower side of a memory address simultaneously, so that while the N-th (where N is a natural number) sector data from one of the upper side and the lower side of the memory address are transferred to the system interface section, the (N+1)th sector data from the other are transferred to the error correcting means.
Also in a memory access control method of an external storage device according to the present invention, the external storage device having a static storage device storing sector data and comprising a first memory storing odd-numbered sector data of sectors of a plurality of continuous sectors of an access object and a second memory storing even-numbered sector data of sectors as the static storage device and error correcting means performing error detection and error correction for the sector data are used. When write access is performed from a host computer to the plurality of continuous sectors, odd-numbered sector data together with error correcting codes are stored in the first memory and also even-numbered sector data together with error correcting codes are stored in the second memory alternately in a size of a sector unit. When a read access is performed from the host computer to the plurality of continuous sectors, the first sector data are read out from the memory and error detection and error correction are performed by the error correcting means and while the first sector data having the error detection and error correction finished are transferred from the first memory to the host computer, the second data are simultaneously read out from the second memory and transferred to the error correcting means. Subsequently, while the second data having the error detection and error correction finished are transferred from the second memory to the host computer, third sector data are simultaneously read out from the first memory and transferred to the error correcting means. In a similar manner, while the N-th sector data having the error detection and error correction finished are transferred to the host computer, the (N+1)th sector data are simultaneously read out and transferred to the error correcting means.
According to the present invention, control means (e.g., a microprocessor) can store a plurality of sector data of a write object in a memory so that the N-th sector data and the (N+1)th sector data can be read out simultaneously. Thereby, at any time, the N-th sector data can be outputted to a system bus by data changing means, and (N+1)th sector data can be simultaneously outputted to error correcting means. Consequently, since a time required for the error detection and error correction for the (N+1)th data can be performed simultaneously during the time the Nth data are outputted to the system bus, the time (as experienced by the external storage arrangement) required for the error detection and error correction for the sector data can be reduced apparently (i.e., made transparent to a host computer).
Also since the error detection and error correction are always executed only for singular sector data which is subsequent to the sector data currently being transferred to the host computer, a single error correcting means may be used well.
The foregoing and other objects, advantages, manner of operation, novel features and a better understanding of the present invention will become apparent from the following detailed description of the preferred embodiments and claims when read in connection with the accompanying drawings, all forming a part of the disclosure hereof this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing embodiments of the invention which are considered preferred embodiments at the time the patent application was filed in order to teach one skilled in the art to make and use the invention, and to otherwise satisfy the best mode disclosure requirements under U.S. patent law, it should be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.